Joint Seminar by UGC Area of Excellence Scheme on Theory, Modeling, and Simulation of Emerging Electronics and Department of Physics
Abstract
This talk provides an overview of the challenges in IC circuit design and verification encountered in the 32nm and 28nm technology nodes. In particular, more focuses are paid to the EDA tools challenge and design flow challenge. The greater challenges undoubtedly provide bigger opportunities to the EDA industry with its continuous technology innovations. Among those key technologies, the in-depth understanding of advanced device models, the realistic model verification at both device level and circuit level, and the much improved simulation speed and performance benefited from the latest multi-core and GPU computer architectures, are just a few good demonstrations.