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Thermal Scanning Probe Lithography for Nano Wire and Photonic Sensors


Speaker:Dr. ZhengMing Wu
Affiliation:SwissLitho AG, Switzerland
Date:May 24, 2019 (Friday)
Time:2:30 p.m.
Venue:Room 522, 5/F, Chong Yuet Ming Physics Building, HKU

Abstract


Thermal Scanning Probe Lithography is a versatile alternative nano-lithography technique to augment standard techniques. The core of the technology is an ultra-sharp, heatable AFM tip which locally evaporates a special resist polymer. It was developed at the IBM Zurich Research Labs and is commercialized as NanoFrazor by the ETH Spin-off SwissLitho.
The same AFM tip is also used for imaging, enabling extremely accurate overlay alignment to existing features, e.g. individual nanowires or 2D-materials (e.g. Molybdenum Disulfide (MoS2), Graphene). These can be located through the resist, much reducing the preparation effort compared to current lithography techniques.
The unique pixel-by-pixel control of the patterning depth allows single step fabrication of complex 2.5D topographies at nanometer vertical resolution. This was demonstrated with optical microcavities in collaboration with the IBM Zurich Research Labs. Microcavities with a shape matched to the optical mode provide superior light confinement over standard disc shapes. Such shaped cavities may also enable novel optical sensors with improved sensitivity.
Compared to the standard methods, Thermal Scanning Probe Lithography has some unique advantages, namely the simple in-situ overlay alignment, the lack of beam damage or charged particle damage, the immediate quality control without development step, and the 2.5D patterning capability. SwissLitho is collaborating closely with its customers to develop fabrication processes for challenging applications.
The figure below shows the application of the fabrication of gates for nanowire transistors (top left), the overlay performance of the fabrication of side gate structures on a nano wire (bottom left) and a demonstrator application for 2.5D patterning of the superior performance of coupled photonic cavities (right).


Figure 1 [1]: Fabrication of gates for nanowire transistors. (a) NanoFrazor topography image of nanowire and source/drain contacts under the resist. (b) cross section through dotted line in (a). (c) patterning result with cross section (d). (e) final gate structures after lift off.

Coffee and tea will be served 20 minutes prior to the seminar.

Anyone interested is welcome to attend.